An Optical Deeection-routed Multiprocessor Interconnect

We describe the design and implementation of a high-bandwidth packet-switched optical interconnect for a shared-memory multipro-cessor with latency-hiding mechanisms. The network has a direct topology and uses deeection routing to resolve contention, obviating elastic buuers and reducing ight latency. Each node is itself a cache-coherent multiprocessor with local memory, hardware to support multiple outstanding remote memory operations and error recovery , a packet routing processor, and a packet switch. Implementation of a prototype distinguishes our work from previous theoretical and experimental work in optical deeection networks. We present implementation details and discuss performance and complexity tradeoos for various link technologies.